(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a dual damascene structure using one processing step of patterning this structure.
(2) Description of the Prior Art
The manufacturing of semiconductor devices requires the application of multiple diverse technical disciplines that collectively enable the continuing advancements of device performance that has been accomplished ever since the initiation of the semiconductor device. These various disciplines address various aspects of the device creation whereby typically a plurality of active circuits is created in a semiconductor substrate. To create a collection of circuits, commonly referred to as Integrated Circuits (IC""s), the individual circuits are interconnected with metal leads. To further increase device density, multiple layers of interconnect metal can be created. These multiple layers of interconnect metal are separated by layers of dielectric or by insulating layers. Adjacent layers of metal lines are interconnected by means of metal contact plugs or vias.
The semiconductor industry has, over the last several decades, been driven by a continued striving to improve device performance, which requires a continued decrease of semiconductor device feature size. In present day semiconductor devices, it is not uncommon to encounter feature size in the deep sub-micron range. With this decrease in device feature size, sub-micron metal interconnects become increasingly more important. A number of different approaches are used in the art for the formation of patterns of interconnect lines, most of these approaches start with the deposition of a patterned layer of dielectric where the pattern in the dielectric forms contact openings between overlying metal and underlying points of electrical contact. A layer of metal is deposited over the layer of dielectric and patterned in accordance with the required pattern of interconnect lines whereby the interconnect lines, where required, align with the underlying contact openings. The patterning of the layer of metal requires the deposition of a layer of photoresist over the layer of metal, the photoresist is exposed typically using photolithographic techniques and etched, typically using a dry etch process. The patterned layer of photoresist is removed after the interconnect metal line pattern has been created leaving the interconnect line pattern in place. For sub-micron metal line sizes, these highlighted processing steps encounter a number of problems that are typical of device sub-miniaturization. These problems are problems of poor step coverage of the deposited metal (the metal should be evenly deposited and should fill the profile for the metal line with equal metal density), problems of etching (using dry etching but metal such as copper and gold are difficult to plasma etch) and problems of step coverage and planarization for the overlying layer of dielectric.
In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings. The first or lowest level of interconnect wires is typically formed as a first step in the process after which a second or overlying level of interconnect wires is deposited over the first level. The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contacts. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure. The two levels of metal wires are connected by openings between the two layers, these openings are filled with metal whereby the openings between the two metal layers are lined up with and match contact points in one or both of the levels of metal lines.
The brief description of the process of metalization that has been given above has been described with reference to the damascene and dual damascene processes which form two widely used approaches in creating metal interconnects. The application of the damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale Integrated (ULSI) devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices.
With increasing device densities, the area that is available for circuit wiring becomes relatively more important as a potential limiting factor in device performance. This has led to the development of multi-layer wiring where the dual damascene structure has found wide use.
For the creation of the single damascene structure, vias only are created. For the creation of the dual damascene, vias are created and conductors are created above the vias. For the dual damascene, special etch procedures can be used to form both the vias and the conductor patterns in the dielectric layer before the deposition of metal and the metal CMP. A thin etch stop layer can be used for this purpose between two layers of dielectric SiO2.
With the damascene process a metal via plug is first formed in a surface, typically the surface of a semi-conductor substrate. A layer of dielectric (for instance SiO2) is deposited over the surface (using for instance PECVD technology); trenches (for metal lines) are formed in the dielectric (using for instance RIE technology). Metal is deposited to fill the trenches; the excess metal on the surface is removed. A planar structure of interconnect lines with metal inlays in the (intra-level) dielectric is achieved in this manner.
For the dual damascene process, the processing steps can follow three approaches.
Approach 1, the via is created first. The vias are formed by resist patterning after which an etch through the triple layer dielectric stack is performed. This is followed by patterning the conductor in the top layer of SiO2 thereby using the SiN as an etch stop layer.
Approach 2. The conductor first process. The conductor patterns is formed by resist patterning and by etching the conductor patterns into the first SiO2 layer thereby using the SiN layer as an etch stop layer. This is followed by via resist patterning and etching through the thin layer of SIN and the second SiO2 layer.
Approach 3. Etch stop layer first. The first SiO2 layer is deposited, followed by the thin layer of SiN as etch stop, followed by the via resist patterning and etching of the SiN layer. This is followed by depositing the top SiO2 layer and then the conductor patterning. In etching the conductor pattern in the top SiO2 layer, the etching process will be stopped by the SiN layer except where the via holes are already opened in the SiN layer thereby completing the via holes etching in the first SiO2 layer simultaneously.
FIGS. 1a and 1b further detail the above.
FIG. 1a gives and overview of the sequence of steps required of forming a Prior Art dual Damascene structure. The numbers referred to in the following description of the formation of the dual Damascene structure relate to the cross section of the completed dual Damascene structure that is shown in FIG. 1b. 
FIG. 1a, 21 shows the creation of the bottom part of the dual Damascene structure by forming a via pattern 22 on a surface 24, this surface 24 can be a semiconductor wafer but is not limited to such. The via pattern 22 is created in the plane of a dielectric layer 20 and forms the lower part of the dual Damascene structure. SiO2 can be used for this dielectric.
FIG. 1a, 22 shows the deposition within plane 30 (FIG. 1b) of a layer of non-metallic material such as poly-silicon on top of the first dielectric 20 and across the vias 22, filling the via openings 22.
FIG. 1a, 23 shows the formation of the top section 41 of the dual Damascene structure by forming a pattern 41 within the plane of the non-metallic layer 30. This pattern 41 mates with the pattern of the previously formed vias 22 (FIG. 1a, 21) but it will be noted that the cross section of the pattern openings 41 within the plane 30 of the non-metallic layer is considerably larger than the cross section of the via openings 22 (FIG. 1a, 21). After pattern 41 has been created and as part of this pattern creation step, the remainder of the non-metallic layer 30 is removed, the pattern 41 remains at this time.
FIG. 1a, 24 shows the deposition and planarization (down to the top surface of pattern 41) of an intra level dielectric (ILD) 50, a poly-silicon can be used for this dielectric.
FIG. 1a, 25 shows the creation of an opening by removing the poly-silicon from the pattern 41 and the vias 22. It is apparent that this opening now has the shape of a T and that the sidewalls of the opening are not straight but show a top section that is larger than the bottom section.
FIG. 1a, 26 shows the cross-section of the dual damascene structure where a barrier 70 has been formed on the sides of the created opening. The opening, which has previously been created by removing the poly-silicon from the pattern 41 and the vias 22, has been filled with a metal. Metal such as tungsten or copper can be used for this latter processing step.
The dual damascene process is being implemented as a standard back-end-of-line (BEOL) process in many manufacturing processes. The typical process involves two masking steps and is achieved using different approaches. In the first approach, a wire mask/etch is performed first while a via mask/etch is performed second. The second approach employs a via mask/etch first while a wire mask/etch is applied second. After patterning the via/wire profile, metal wires are defined using a CMP process. The second approach (via first, wire second) has the advantage of performing the (difficult) step of via masking over a planar dielectric surface. The disadvantages of the present dual damascene process that has been highlighted above are:
the process is a two step process that is expensive and time consuming
the process is prone to misalignment between the wire profile and the via plug
the removal of resist and etch residue from deep trenches in the substrate during the second masking and development sequence may become difficult for devices of significantly reduced device dimensions.
It is therefore desirable to provide a process of creating dual damascene structures that is not prone to the above indicated problems or potential problems. The invention provides such a process by making this process a one step process whereby no misalignment (between via plug and the wire profile) occurs and where no deep trenches are formed in the substrate.
U.S. Pat. No. 5,821,169 (Nguyen et al.) show a dual damascene process using a multi-level resist profile exposed using 2 optical masks. This patent is extremely close to the invention. This novel patent describes a method that is used to transfer a photoresist step profile to an underlying substrate. The invention concentrates on problems of the etch process that transfers the step profile.
U.S. Pat. No. 5,753,417 (Ulrich) shows a one PR method for forming a Dual Damascene opening. Ulrich uses 2 optical masks to form the multi-level resist layer in contrasts to the invention""s 1 optical mask. Ulrich cited a gray tone mask in the xe2x80x9cOther referencesxe2x80x9d section. Overall, this patent is very close to the invention. The invention uses a multiple exposure masking system for forming a multi-level resist profile. The invention also describes a double exposure method, that it is uses two masks that have different transmission values.
U.S. Pat. No. 5,535,253 (Park et al.) discloses a Dual damascene shaped photoresist layer 12 (See FIG. 1C) formed using the same optical mask as the invention. However, Park forms a T-shaped gate, not a DD opening.
U.S. Pat. No. 5,877,075 (Dai et al.) shows a dual damascene process using 1 photoresist layer. The dual damascene process of this invention uses a single photoresist process. The invention describes a double exposure technique that uses two masks.
U.S. Pat. No. 5,869,395 (Yim) shows a dual damascene process using photoresist layer.
The principle objective of the invention is to provide a one step process for the creation of a dual damascene structure.
Another objective of the invention is to avoid problems of pattern misalignment in creating a dual damascene structure.
Yet another objective of the invention is to prevent potential problems of residue removal from the surface of a substrate in which a dual damascene structure has been created by avoiding the need for deep trenches in the surface of the substrate for the creation of dual damascene structures.
A still further objective of the invention is to reduce the time that is required to form a dual damascene structure.
In accordance with the objectives of the invention a new method is provided for the creation of a dual damascene structure. The method of the invention uses a gray tone mask to form dual damascene trenches in one single masking and etch step. The gray tone mask technology allows for a photoresist patterning process after which the photoresist profile can be transferred into the underlying substrate by a plasma etch or ion milling process. By making the photoresist profile equal to the profile of a dual damascene structure, the dual damascene profile can be created in the surface of a substrate.